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contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any mean s, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team. precautions for light light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characte ristics of semiconductor devices when irradiated with light. consequently, the users of the packages which may expose chips to external light such as cob, cog, tcp and cof must consider effective methods to block out light from reaching the ic on all parts of the surface area, the top, bottom and the sides of the chip. follow the precautions below when using the products. 1. consider and verify the protection of penetrating light to the ic at substrate ( board or glass) or product design stage. 2. always test and inspect products under the environment with no penetration of light. S6B1400X 1 04 seg / 65 com driver & controller for stn lcd mar . 2002 ver . 0.0
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 2 s6b 1400x specification revision history version content date 0.0 initial v ersion 2002.03
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 3 co ntents introdu ction ................................ ................................ ................................ ................................ ............ 1 features ................................ ................................ ................................ ................................ .................... 1 block diagram ................................ ................................ ................................ ................................ ......... 3 pad configuration ................................ ................................ ................................ ................................ . 4 pad center coordinat es ................................ ................................ ................................ ...................... 6 power supply ................................ ................................ ................................ ................................ .... 8 lcd driver supply ................................ ................................ ................................ ............................ 8 system control ................................ ................................ ................................ ................................ 9 microprocessor inter face ................................ ................................ ................................ ......... 10 lcd driver outputs ................................ ................................ ................................ ......................... 12 functional descripti on ................................ ................................ ................................ ....................... 13 microprocessor inter face ................................ ................................ ................................ ......... 13 display data ram (dd ram) ................................ ................................ ................................ .............. 18 lcd display circuits ................................ ................................ ................................ ....................... 21 lcd driver circuits ................................ ................................ ................................ ......................... 23 power supply circuit s ................................ ................................ ................................ .................. 24 reset circuit ................................ ................................ ................................ ................................ .... 30 instruction descript ion ................................ ................................ ................................ ...................... 31 specifications ................................ ................................ ................................ ................................ ......... 46 absolute maximum rat ings ................................ ................................ ................................ ........... 46 dc characteristics ................................ ................................ ................................ ........................ 47 ac characteristics ................................ ................................ ................................ ......................... 50 reference applicatio ns ................................ ................................ ................................ ...................... 54 microprocessor inter face ................................ ................................ ................................ ......... 54 connections between S6B1400X and lcd pan el ................................ ................................ ....... 56

s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 1 introduc tion the S6B1400X is a single - chip driver & controller lsi for graphic dot - matrix liquid crystal display systems. this chip can be connected directly to a microprocessor, accepts serial or 8 - bit parallel display data from the microprocessor, stores the dis play data in an on - chip display data ram of 65 x 1 04 bits and generates a liquid crystal display drive signal independent of the microprocessor . it provides a high - flexible display section due to 1 - to - 1 correspondence between on - chip display data ram bits and lcd panel pixels. it contains 6 5 common driver circuits and 1 04 segment driver circuits, so that a single chip can drive a 65 x 104 dot display. this chip is able to minimize power consumption because it performs display data ram read/write operation w ith no external operation clock . in addition, because it contains power supply circuits necessary to drive liquid crystal, which is a display clock oscillator circuit, high performance voltage converter circuit, high - accuracy voltage regulator circuit, low power consumption voltage divider resistors and op - amp for liquid crystal driver power voltage, it is possible to make the lowest power consumption display system with the fewest components for high performance portable systems . features display driver ou tput circuits - 6 5 common outputs and 1 04 segment outputs on - chip display data ram - capacity: 65 x 1 04 = 6 , 760 bits - ram bit data ? 1 ? : a dot of display is illuminated - ram bit data ? 0 ? : a dot of display is not illuminated applicable duty ratios d uty ratio a pplicable lcd bias maximum display area 1/ 6 5 1/ 7 or 1/ 9 6 5 1 04 1/55 1/6 or 1/8 55 104 1/49 1/6 or 1/8 49 104 1/33 1/5 or 1/6 33 104 microprocessor interface - high - speed 8 - bit parallel bi - directional interface with 6800 - series or 8080 - seri es - spi ( serial peripheral i nterface ) available. (only write operation) various function set - display on / off, set initial display line, set page address, set column address, read status, write/read d isplay data, select segment driver output, reverse di splay on / off, entire display on / off, select lcd bias, set/reset modify - read, select common driver output, control display power circuit, select internal regulator resistor ratio for v lcd voltage regulation, electronic volume, set static indicator state . - h/w and s/w reset available - static drive circuit equipped internally for indicators with 4 flashing mode
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 2 built - in a nalog c ircuit - on - chip oscillator circuit for display clock - high performance v oltage converter ( with booster ratios of x 3 and x 4) - high accuracy voltage regulator (temperature coefficient: - 0.0 5 0.03 %/ c or external input ) - electronic contrast control function (64 steps) - vref = 2.1v 3% (v lcd voltage adjustment voltage) - high performance v oltage follower (v1 to v4 voltage divider resisto rs and op - amp for increasing drive capacity) operating voltage range - supply voltage (v dd ): 2.4 to 3.6 v - booster input voltage (vci): v dd to 3.0 v ( x 4), v dd to 3.6 v ( x 3) - lcd driving voltage (v lcd ): 4. 5 to 9. 0 v low power consumption - operating power: 120 m a t yp ical (c onditions: v dd = 3v, x 3 boosting (vci = v dd ), v lcd = 7.6 v, internal power supply on , display o ff and normal mode is selected ) - standby power: 10 m a max imum (d uring power save[s t andby] mode) operating temperatures - wide range of operating temperatures : - 40 to 85 c cmos process package type - gold bumped chip
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 3 block diagram cl frs fr duty0 duty1 v dd v ss hpmb vlcd vr intrs ref vext vci dcdc4b v / c circuit v / r circuit v / f circuit 33 common driver circuits mpu interface (parallel & serial) instruction decoder bus holder column address circuit line addres s circuit page address circuit display data ram 65 x 1 04 = 6 , 76 0 bits display data control circuit display timing generator circuit common output controller circuit db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) c68 resetb p s rw_wrb e_rdb r s c s2 cs1b com31 : com0 coms0 seg103 seg102 seg101 : : seg2 seg1 seg0 com32 : com63 coms1 oscillator 1 04 segment driver circuits 33 common driver circuits i/o buffer status register instruction register figure 1 . block diagram
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 4 pad configuration eee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee eee y 123 1 S6B1400X (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeee 300 125 124 301 e e tom figure 2 . S6B1400X chip configuration table 1 . S6B1400X pad dimensions size item pad no. x y unit chip size - 11080 1970 chip height - 470u(+/ - 10) 1 to 123 70(min.) pad pitch 125 to 300 60(min.) 1 to 123 50 100 124, 301 110 40 bumped pad size ( top) 125 to 300 40 110 m m bumped pad height a ll pad 1 4 (typ.)
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 5 cog align key coordinate ilb align key coordinate (with gold bump *) 30 m m 30 m m 30 m m (-5295, -830) 30 m m 30 m m 30 m m (5425, 845.05) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (-5470, 915) (5460, -895) * when des igning c og pattern, ito pattern must be prohibited on ilb align key, dummy pads , test pads. if ito pattern is used for routing over th ese area, it can be happened pattern - short through bumped pattern on these area . tom (teg on main chip) coordinate t he t om ha s test items for process evaluation. there are many bumped pads in this area as like main chip. so when designing cog pattern, ito pattern must be prohibited on this area (tom). if ito pattern is used for routing over this area, it can be happened pattern - short through bumped pad on tom. 600 m m 220 m m (4480,-915) (5080 ,-695)
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 6 pad center coordinat es table 2 . p ad center coordinates [unit: m m] x y x y x y 1 dummy<0> -5020 -870 51 vss -1088 -870 101 vss 2412 -870 2 frs -4950 -870 52 c68 -1018 -870 102 vr 2482 -870 3 fri -4880 -870 53 vdd -948 -870 103 vss 2552 -870 4 cl -4810 -870 54 e_rdb -878 -870 104 testa0 2622 -870 5 test -4740 -870 55 rw_wrb -808 -870 105 testb0 2692 -870 6 vdd -4670 -870 56 vss -738 -870 106 vss 2762 -870 7 vdd -4600 -870 57 cs1b -668 -870 107 vlcd 2832 -870 8 vdd -4530 -870 58 cs2 -598 -870 108 vlcd 2902 -870 9 vdd -4460 -870 59 vdd -528 -870 109 vlcd 2972 -870 10 vdd -4390 -870 60 vci -458 -870 110 vlcd 3042 -870 11 vdd -4320 -870 61 vci -388 -870 111 vlcd 3112 -870 12 vdd -4250 -870 62 vci -318 -870 112 vlcd 3182 -870 13 vdd -4180 -870 63 vci -248 -870 113 testa1 3252 -870 14 vdd -4110 -870 64 vci -178 -870 114 testb1 3322 -870 15 vdd -4040 -870 65 vci -108 -870 115 testa2 3392 -870 16 vdd -3970 -870 66 vci -38 -870 116 testb2 3462 -870 17 vdd -3900 -870 67 vci 32 -870 117 testa3 3532 -870 18 vci -3830 -870 68 vci 102 -870 118 testb3 3602 -870 19 vci -3760 -870 69 vci 172 -870 119 testa4 3888 -870 20 vci -3690 -870 70 vci 242 -870 120 testb4 3958 -870 21 vci -3620 -870 71 vci 312 -870 121 dummy<5> 4244 -870 22 vci -3550 -870 72 vdd 382 -870 122 resetb 4314 -870 23 vci -3480 -870 73 vext 452 -870 123 dummy<6> 4384 -870 24 vci -3410 -870 74 vss 522 -870 124 dummy<7> 5420 722 25 vci -3340 -870 75 ref 592 -870 125 dummy<8> 5284 838 26 vci -3270 -870 76 vdd 662 -870 126 com<31> 5224 838 27 vci -3200 -870 77 dcdc4b 732 -870 127 com<30> 5164 838 28 vci -3130 -870 78 vss 802 -870 128 com<29> 5104 838 29 vci -3060 -870 79 hpmb 872 -870 129 com<28> 5044 838 30 vdd -2990 -870 80 vdd 942 -870 130 com<27> 4984 838 31 db<0> -2920 -870 81 intrs 1012 -870 131 com<26> 4924 838 32 db<1> -2850 -870 82 vss 1082 -870 132 com<25> 4864 838 33 db<2> -2780 -870 83 vss 1152 -870 133 com<24> 4804 838 34 db<3> -2710 -870 84 vss 1222 -870 134 com<23> 4744 838 35 db<4> -2640 -870 85 vss 1292 -870 135 com<22> 4684 838 36 db<5> -2570 -870 86 vss 1362 -870 136 com<21> 4624 838 37 db<6> -2500 -870 87 vss 1432 -870 137 com<20> 4564 838 38 dummy<1> -2430 -870 88 vss 1502 -870 138 com<19> 4504 838 39 dummy<2> -2144 -870 89 vss 1572 -870 139 com<18> 4444 838 40 db<7> -2074 -870 90 vss 1642 -870 140 com<17> 4384 838 41 dummy<3> -2004 -870 91 vss 1712 -870 141 com<16> 4324 838 42 dummy<4> -1718 -870 92 vss 1782 -870 142 com<15> 4264 838 43 vss -1648 -870 93 vss 1852 -870 143 com<14> 4204 838 44 duty0 -1578 -870 94 vss 1922 -870 144 com<13> 4144 838 45 vdd -1508 -870 95 vss 1992 -870 145 com<12> 4084 838 46 duty1 -1438 -870 96 vss 2062 -870 146 com<11> 4024 838 47 vss -1368 -870 97 vss 2132 -870 147 com<10> 3964 838 48 rs -1298 -870 98 vss 2202 -870 148 com<9> 3904 838 49 vdd -1228 -870 99 vss 2272 -870 149 com<8> 3844 838 50 ps -1158 -870 100 vss 2342 -870 150 com<7> 3784 838 pad no. pad name coordinate pad no. pad name coordinate pad no. pad name coordinate
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 7 table 2 . p ad center coordinates (continued) [unit: m m] x y x y x y 151 com<6> 3724 838 201 seg<63> 724 838 251 seg<13> -2276 838 152 com<5> 3664 838 202 seg<62> 664 838 252 seg<12> -2336 838 153 com<4> 3604 838 203 seg<61> 604 838 253 seg<11> -2396 838 154 com<3> 3544 838 204 seg<60> 544 838 254 seg<10> -2456 838 155 com<2> 3484 838 205 seg<59> 484 838 255 seg<9> -2516 838 156 com<1> 3424 838 206 seg<58> 424 838 256 seg<8> -2576 838 157 com<0> 3364 838 207 seg<57> 364 838 257 seg<7> -2636 838 158 coms<0> 3304 838 208 seg<56> 304 838 258 seg<6> -2696 838 159 dummy<9> 3244 838 209 seg<55> 244 838 259 seg<5> -2756 838 160 dummy<10> 3184 838 210 seg<54> 184 838 260 seg<4> -2816 838 161 seg<103> 3124 838 211 seg<53> 124 838 261 seg<3> -2876 838 162 seg<102> 3064 838 212 seg<52> 64 838 262 seg<2> -2936 838 163 seg<101> 3004 838 213 seg<51> 4 838 263 seg<1> -2996 838 164 seg<100> 2944 838 214 seg<50> -56 838 264 seg<0> -3056 838 165 seg<99> 2884 838 215 seg<49> -116 838 265 dummy<11> -3116 838 166 seg<98> 2824 838 216 seg<48> -176 838 266 dummy<12> -3176 838 167 seg<97> 2764 838 217 seg<47> -236 838 267 com<32> -3236 838 168 seg<96> 2704 838 218 seg<46> -296 838 268 com<33> -3296 838 169 seg<95> 2644 838 219 seg<45> -356 838 269 com<34> -3356 838 170 seg<94> 2584 838 220 seg<44> -416 838 270 com<35> -3416 838 171 seg<93> 2524 838 221 seg<43> -476 838 271 com<36> -3476 838 172 seg<92> 2464 838 222 seg<42> -536 838 272 com<37> -3536 838 173 seg<91> 2404 838 223 seg<41> -596 838 273 com<38> -3596 838 174 seg<90> 2344 838 224 seg<40> -656 838 274 com<39> -3656 838 175 seg<89> 2284 838 225 seg<39> -716 838 275 com<40> -3716 838 176 seg<88> 2224 838 226 seg<38> -776 838 276 com<41> -3776 838 177 seg<87> 2164 838 227 seg<37> -836 838 277 com<42> -3836 838 178 seg<86> 2104 838 228 seg<36> -896 838 278 com<43> -3896 838 179 seg<85> 2044 838 229 seg<35> -956 838 279 com<44> -3956 838 180 seg<84> 1984 838 230 seg<34> -1016 838 280 com<45> -4016 838 181 seg<83> 1924 838 231 seg<33> -1076 838 281 com<46> -4076 838 182 seg<82> 1864 838 232 seg<32> -1136 838 282 com<47> -4136 838 183 seg<81> 1804 838 233 seg<31> -1196 838 283 com<48> -4196 838 184 seg<80> 1744 838 234 seg<30> -1256 838 284 com<49> -4256 838 185 seg<79> 1684 838 235 seg<29> -1316 838 285 com<50> -4316 838 186 seg<78> 1624 838 236 seg<28> -1376 838 286 com<51> -4376 838 187 seg<77> 1564 838 237 seg<27> -1436 838 287 com<52> -4436 838 188 seg<76> 1504 838 238 seg<26> -1496 838 288 com<53> -4496 838 189 seg<75> 1444 838 239 seg<25> -1556 838 289 com<54> -4556 838 190 seg<74> 1384 838 240 seg<24> -1616 838 290 com<55> -4616 838 191 seg<73> 1324 838 241 seg<23> -1676 838 291 com<56> -4676 838 192 seg<72> 1264 838 242 seg<22> -1736 838 292 com<57> -4736 838 193 seg<71> 1204 838 243 seg<21> -1796 838 293 com<58> -4796 838 194 seg<70> 1144 838 244 seg<20> -1856 838 294 com<59> -4856 838 195 seg<69> 1084 838 245 seg<19> -1916 838 295 com<60> -4916 838 196 seg<68> 1024 838 246 seg<18> -1976 838 296 com<61> -4976 838 197 seg<67> 964 838 247 seg<17> -2036 838 297 com<62> -5036 838 198 seg<66> 904 838 248 seg<16> -2096 838 298 com<63> -5096 838 199 seg<65> 844 838 249 seg<15> -2156 838 299 coms<1> -5156 838 200 seg<64> 784 838 250 seg<14> -2216 838 300 dummy<13> -5216 838 301 dummy<14> -5420 662 coordinate pad no. pad name coordinate pad no. pad name coordinate pad no. pad name
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 8 pin description power supply tabl e 3. power supply pins description name i/o description vdd supply power supply v ss supply ground lcd driver supply table 4. lcd driver supply pins description name i/o description v lcd o lcd power supply output pin connect this pin to v ss through cap acitor.(capacitor is greater than 1 m f) dcdc4b i 4 times boosting circuit enable input pin - dcdc4b = " h ": 3 times boosting - dcdc4b = " l ": 4 times boosting vr i v lcd voltage adjustment pin it is valid only when internal voltage regulator resistors are not used (intrs = ?l?) . vci i this is the reference voltage for the voltage converter circuit for the lcd driving. whether internal voltage converter use or not use, this pin should be fixed. the voltage should have the following range: 2.4v vci 3.6v ( vci 3 v dd ) vext i this is the external - input reference voltage (v ref ) for the internal voltage regulator. it is valid only when external v ref is used ( ref = ?l?) . when using internal v ref, this pin is open ref i select the external v ref voltage via ve xt pin - ref = " l ": u sing the external v ref - ref = " h ": u sing the internal v ref
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 9 system control table 5. system control pins description name i/o description cl o display clock output pin frs o static driver segment output pin this pin is used togethe r with the fr pin. fr o static driver common output pin this pin is used together with the frs pin. intrs i internal resistor select pin this pin selects the resistors for adjusting v lcd voltage level. - intrs = ?h?: the internal resistors are used - i ntrs = ?l?: the external resistors are used v lcd voltage is controlled by vr pin and external resistive divider. (* refer to page 28) the lcd driver duty ratio depends on the following table . duty1 duty0 duty r atio l l 1/33 l h 1/49 h l 1/55 h h 1/65 duty0 duty1 i hpm b i power control pin of the power supply circuit s for lcd driver. - hpm b = ? h ?: normal mode - hpm b = ? l ?: high power mode
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 10 microprocessor inter face table 6. microprocesso r i nterface pins description name i/o description resetb i reset input pin when resetb is ?l?, initialization is executed. parallel / serial data input select input ps interface mode chip s elect data / instruction data read / write serial clock h parallel cs1b, cs2 rs db0 to db7 e_rdb rw_wrb - l serial cs1b, cs2 rs sid (db7) write only sclk (db6) ps i *note: in serial mode , it is impossible to read data from the on - chip ram. and db0 to db5 are high impedance and e_rdb and rw_wrb must be f ixed to either ?h? or ?l?. c68 i microprocessor interface select input pin - ps = ? h ? , c68 = "h": 6800 - series parallel mpu interface - ps = ? h ? , c68 = "l": 8080 - series parallel mpu interface - ps = ? l ? , c68 = "h": 4 pin - spi serial mpu interface - ps = ? l ? , c68 = "l": 3 pin - spi serial mpu interface cs1b cs2 i chip select input pins data/instruction i/o is enabled only when cs1b is ?l? and cs2 is ?h?. when chip select is non - active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data * this pin must be fixed to either ? h ? or ? l ? in case of 3 pin - spi serial mpu interface mode read / write execution control pin c68 mpu type rw_wrb description h 6800 - series rw read / write control input pin - rw _wrb = ?h?: read - rw _wrb = ?l?: write l 8080 - series / wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the rw_ wr b signal. rw_wrb i
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 11 table 6. microprocessor interface pins d escription (continued) name i/o description read / write execution control pin c68 mpu type e_rdb description h 6800 - series e read/write control input pin - rw _wrb = ?h?: when e _rdb is ?h?, db0 to db7 are in an output status. - rw _wrb = ?l?: the data on db0 to db7 are l atched at the falling edge of the e _rdb signal. l 8080 - series / rd read enable clock input pin when e_ rd b is ?l?, db0 to db7 are in an output status. e_rdb i db0 to db7 i/o 8 - bit bi - directional data bus that is connected to the standard 8 - bit microprocessor data bus. when the serial interface selected (ps = "l"), - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid) when chip select is not active, db0 to db7 may be hig h impedance. tests i/o these are pins for chip test. they are set to open. note: dummys ? these pins should be opened (floated).
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 12 lcd driver outputs table 7. lcd driver output pins description name i/o description lcd segment driver outputs the display data and the fr signal control the output voltage of segment driver. segment driver output voltage display data fr normal display reverse display h h v lcd v2 h l v ss v3 l h v2 v lcd l l v 3 v ss power save mode v ss v ss seg 0 t o seg 103 o lcd common driver outputs the internal scanning data and fr signal control the output voltage of common driver. scan data fr common driver output voltage h h v ss h l v lcd l h v1 l l v4 power save mode v ss com 0 to com 63 o coms 0 coms1 o common output for the icons the output signals of two pins are same. when not used, these pins should be left o pen.
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 13 functional descripti on microprocessor inter face chip select input there are cs1b and cs2 pins fo r chip selection. the S6B1400X can interface with an mpu only when cs1b is ?l? and cs2 is ?h?. when these pins are set to any other combination, rs, e_rdb, and rw_wrb inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial inter face, the internal shift register and the counter are reset. parallel / serial interface S6B1400X has four types of interface with an mpu, which are two serial and two parallel interfaces. this parallel or serial interface is determined by ps pin as shown in table 8 . table 8 . parallel / serial interface mode ps type cs1b cs2 c68 interface mode h 6800 - series mpu mode h parallel cs1b cs2 l 8080 - series mpu mode h 4 pin - spi serial mpu mode l serial cs1b cs2 l 3 pin - spi s erial mpu mode parallel int erface (ps = "h") the 8 - bit bi - directional data bus is used in parallel interface and the type of mpu is selected by c68 as shown in table 9 . the type of data transfer is determined by signals at rs, e_rdb and rw_wrb as shown in table 10 . table 9 . micropro cessor selection for parallel interface c68 cs1b cs2 rs e_rdb rw_wrb db0 to db7 mpu bus h cs1b cs2 rs e rw db0 to db7 6800 - series l cs1b cs2 rs / rd / wr db0 to db7 8080 - series table 10 . parallel data transfer common 6800 - series 8080 - series rs e_rdb (e) rw_wrb (rw) e_rdb ( / rd) rw_wrb ( / wr) description h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 14 cs1b cs2 rs rw_wrb e_rdb db command write data w rite status read data read figure 2 - 1. 6800 - serie s mpu interface protocol (ps= ? h ? , c68= ? h ? ) cs1b cs2 rs rw_wrb e_rdb db command write data w rite status read data read figure 2 - 2. 8080 - series mpu interface protocol (ps= ? h ? , c68= ? l ? )
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 15 serial interface (ps = "l") when the S6B1400X is active (cs1b= ? l ?, cs2= ? h ? ), serial data (db7) and serial clock (db6 ) inputs are enabled. and not active, the internal 8 - bit shift register and the 3 - bit counter are reset. the display data/command indication may be controlled either via software or the register select (rs) pin, based on the setting of c68. when the rs pin is used (ps = ? h ? ), data is display data when rs is high, and command data when rs is low. when rs is not used (c68 = ? l ? ), the lcd driver will receive command from mpu by default. if messages on the data pin are data rather than command, m p u should send data direction command (1 0000 000) to control the data direction and then one more command to define the number of data bytes will be write. after these two continuous commands are sending, the following messages will be data rather than command. serial dat a can be read on the rising edge of serial clock going into db6 and processed as 8 - bit parallel data on the eighth serial clock. and the ddram column address pointer will be increased by one automatically. the next bytes after the display data string is ha ndled as command data. s erial data can be read on the rising edge of serial clock going into db6 and processed as 8 - bit parallel data on the eighth serial clock . since the clock signal ( db6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. t he serial interface type is selected by setting c68 as shown in table 11. table 11 . parallel / serial interface mode serial mode ps c68 chip select register select serial data / clock input 4 pin spi serial mode l h cs1b, cs2 rs pin db7 / db6 3 pin spi serial mode l l cs1b, cs2 software db7 / db6 4 pin spi serial interface (ps = "l" , c68 = " h ") in 4 - pin serial interface mode, rs pin is used for indicating whether serial data input is di splay or instruction data. d ata is display data when rs is high and instruction data when rs is low. cs1b cs2 sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 3 . 4 pin spi s erial interface timing (rs used)
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 16 3 pin - spi interface (ps = "l" , c68 = " l ") in 3 - pin spi interface mode, the pre - defined instruction called display data length, is used to indicate whether serial data input is display or instruction data instead of rs pin. the data is handled as instruction data until the display data length instructi on is issued. this display data length instruction consists of two bytes instruction. the first byte instruction enables the next instruction to be valid, and the data of the second byte indicates that a specified number of display data bytes (1 to 256) ar e to be transmitted. the next byte after the display data string is handled as instruction data. for details, refers to figure 4. sclk cs1b / cs2 829 830 831 ~ ~ ~ ~ 0 0 1 7 8 ~ ~ 15 ~ ~ 23 sid msb data in page lsb ddc no. of data 3 byte (1) 2 byte (2) 104 byte 0 (1) set page and column address. set page address : 1 0 1 1 p3 p2 p1 p0 set column address msb : 0 0 0 1 0 y6 y5 y4 set column address lsb : 0 0 0 0 y3 y2 y1 y0 (2) set ddc(data direction command) and no. of data bytes. set data direction command( for spi mode only): 1 0 0 0 0 0 0 0 set no. of data bytes(ddl) : d7 d6 d5 d4 d3d2d1d0 figure 4 . 3 pin spi timing (rs is not used) this command is used in 3 - p in spi mode only. it will be two continuous commands, the first byte control s the data direction and inform s the lcd driver the second byte will be number of data bytes will be write. after these two commands sending out, the following messages will be dat a. if data is stopped in transmitting, i t i s not valid data. new d ata will be transferred serially with most significant bit first. *notes: - in spite of transmission of d ata, if cs1b will be disable, state terminates abnormally. next state is initial ized. - the number of writing display data = ddl register value + 1 busy flag the busy flag indicates whether the S6B1400X is operating or not. when db7 is ?h? in read status operation, this device is in busy status and will accept only read status in struction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 17 data transfer the S6B1400X uses bus holder and internal data bus for data transfer with the mpu. when wri ting data from the mpu to on - chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 5 . and when reading data from on - chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) an d the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 6 . this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of th e specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. rs rw_ wr b db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals rw_ wr b bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 5 . write timing rs rw_ wr b e_ rd b db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals rw_ wr b e_ rd b bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 d(n+2) figure 6 . read timing
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 18 display data ram (dd ram) the display data ram stores pixel data for the lcd. it is 65 - row by 1 04 - column addressable array. each pixel can be selected when the page and column addresses are specified. the 65 r ows are divided into 8 pages of 8 lines and the 9 th page with a single line (db0 only). data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd commo n lines as shown in figure 7 . the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicke r. com 0 - - com 1 - - com 2 - - com 3 - - com 4 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 display data ram lcd display figure 7 . ram - to - lcd data transfer page address circuit this circuit is for providing a page address to display data ram shown in figure 9 . it incorporates 4 - bit page address register changed by only the ?set page? instruction. page address 8 (db3 is ?h?, but db2, db1 and db0 are ?l?) is a special ram area for the icons and display data db0 is only valid. when page address is above 8, it is impossible to access to on - chip ram. line address circuit this circuit assigns ddram a line address corresponding to the first line (com 0 ) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on - chip ram as sh own in figure 9 . it incorporates 6 - bit line address register changed by only the initial display line instruction and 6 - bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by c l signal and generates the line address for transferring the 1 04 - bit ram data to the display data latch circuit. however, display data of icons are not scrolled because the mpu cannot access line address of icons.
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 19 column address circuit column address cir cuit has a 7 - bit preset counter that provides column address to the display data ram as shown in figure 9 . when set column address msb / lsb instruction is issued, 7 - bit [y 6 :y0] is updated. and, since this address is increased by 1 each a read or write dat a instruction, microprocessor can access the display data continuously. however, the counter is not incre as ed and locked if a non - existing address above 67 h. it is unlocked if a column address is set again by set column address msb/lsb instruction. and t he column address counter is independent of page address register. adc select instruction makes it possible to invert the relationship between the column address and the segment outputs. it is necessary to rewrite the display data on built - in ram after issui ng adc select instruction. refer to the following figure 8 . seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 100 seg 101 seg 102 seg 103 column address [y 7 :y0] 00h 01h 02h 03h ... ... 64 h 65 h 66 h 67 h display data 1 0 1 0 1 1 0 0 lcd panel display ( adc = 0 ) ... ... lcd panel display ( adc = 1 ) ... ... figure 8 . the relationship b etween t he column address a nd t he segment outputs segment control circuit this circuit controls the display data by the display on / off, reverse display on / off and entire display on / off instructions without changing the data in the display data ram.
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 20 start 1/55 duty page0 page2 page1 page4 page3 page6 page5 page7 page8 line address com output page address db3 db0 db1 db2 data - - - - - - - - - - seg103 seg102 seg1 seg0 seg101 seg100 seg99 seg98 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 28h 27h 26h 25h 24h 23h 22h 21h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 38h 37h 36h 35h 34h 33h 32h 31h 39h 3ah 3bh 3ch 3dh 3eh 3fh coms 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1/49 duty 1/33 duty com0 67 65 63 64 62 00 - 02 04 03 05 05 04 03 01 02 00 62 63 64 66 65 67 01 66 when the initial display line address is 1c[hex] com9 com8 com7 com6 com5 com3 com4 com2 com1 com10 com19 com18 com17 com16 com15 com13 com14 com12 com11 com20 com29 com28 com27 com26 com25 com23 com24 com22 com21 com30 com39 com38 com37 com36 com35 com33 com34 com32 com31 com40 com49 com48 com47 com46 com45 com43 com44 com42 com41 com50 com59 com58 com57 com56 com55 com53 com54 com52 com51 com60 com63 com62 com61 figure 9 . display data ram map
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 21 lcd display circuits oscillator this is com pletely on - chip oscillator and its frequency is nearly independent of v dd . this oscillator signal is used in display timing generation circuit. display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl generated by oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. the line address of on - chip ram is generated in synchronization with the display clock (cl) and the 1 04 - bit display data is latch ed by the display data latch circuit in synchronization with the display clock. the display data which is read to the lcd driver is completely independent of the access to the display data ram from the microprocessor. the lcd ac signal, fr is generated fro m the display clock. 2 - frame ac driver waveform s with internal timing signal are shown in figure 10 . com0 vlcd v1 v2 v3 v4 v ss com1 vlcd v1 v2 v3 v4 v ss vlcd v1 v2 v3 v4 v ss segn 64 65 1 2 3 4 5 6 7 8 9 10 11 12 58 59 60 61 62 63 64 65 1 2 3 4 5 6 cl fr figure 10 . 2 - frame ac driving waveform ( d uty ratio = 1/ 6 5)
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 22 common output control circuit this circuit controls the relationsh ip between the number of common output and specified duty ratio. shl select instruction specifies the scanning direction of the common output pins . table 12. the relationship between duty ratio and common output common o utput p ins duty shl com [0:15] c om [16:23] com [24:26] com [27:36] com [37:39] com [40:47] com [48:63] coms 0 com[0:15] *nc com[16:31] 1/33 1 com[31:16] *nc com[15:0] coms 0 com[0:23] *nc com[24:47] 1/49 1 com[47:24] *nc com[23:0] coms 0 com[0:26] *nc com[27:53 ] 1/55 1 co m[53:27] *nc com[26:0] coms 0 com[0:63] 1/65 1 com[63:0] coms *nc: no connection
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 23 lcd driver circuit s this driver circuit is configured by 66 - c hannel (including 2 coms channels) common driver and 1 04 - channel segment driver. this lcd panel driver voltage d epends on the combination of display data and fr signal. com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com1 0 com1 1 com1 2 com1 3 com1 4 com 15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg 2 seg 1 seg 0 com 2 com 0 com 1 f r v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v dd v ss figure 11 . segment and common timing
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 24 power supply circuit s the power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with lo w - power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are controlled by power control instruction. for details, refers to ? instruction description ? . voltage con verter circuits these circuits boost up the electric potential between vci and v ss to 3 or 4 times toward positive side . vout = 3 vci v ss vci vci dcdc4b vout = 4 vci v ss vci vci vdd vdd vci dcdc4b vci vdd v ss figure 12 . three times boosting circuit figure 13 . four times boosting circuit * the vci voltage range must be set so that the vout (voltage converter output) does not exceed the absolute maximum rating value
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 25 voltage regulator circuits the function of the internal voltage regulator circuit s is to determine liquid crystal operating voltage, v lcd , by adjusting resistors, ra and rb, within the range of |v lcd | < | vout |. because vout is the operating voltage of operational - amplifier circuits shown in figure 14 , it is necessary to be applied inte rnally. for the eq. 1, we determine v lcd by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 2, where the parameter a is the value selected by instructi on, "set reference voltage register", within the range 0 to 63. v ref voltage at ta = 25 c is shown in table 13 . rb v lcd = ( 1 + ? ? ? ? ) x v ev [v] ------ ( eq. 1 ) ra (63 - a ) v ev = ( 1 - ? ? ? ? ? ? ) x v ref [v] ------ ( eq. 2 ) 162 table 13. v ref voltage at ta = 25 c ref temp. coefficient v ref [v] h - 0.05% / c 2.1 l external i nput vext table 14. electronic contrast control register (64 steps) s v5 s v4 s v3 s v2 s v1 s v0 reference voltage p arameter ( a ) v lcd contrast 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 0 0 0 0 0 32 ( d efault) : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 minimum : : : : : maximum low : : : : : high
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 26 v ev gnd ra rb v ss vr v lcd vout + - v ref v ext intrs inside chip ref figure 14 . internal v oltage r egulator c ircuit
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 27 in case of using internal resistors, ra and rb (intrs = "h") when intrs pin is ?h?, resistor ra is connected internally between vr pin and v ss , and rb is connected between v lcd and vr. we determine v lcd by two instructions, "regulator resistor select" and "set reference voltage". table 15 . internal rb / ra ratio depending on 3 - bit data (r2 r1 r0) 3 - bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / ra) 3.0 3.5 4.0 4.5 5.0 5.5 not available not available the following figure shows v lcd voltage measured by adjusting internal regulator re s ist o r ratio (rb / ra) and 6 - bit electronic volume registers for each temperature coefficien t at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0 8 16 24 32 40 48 56 electronic volume level v0 [v] (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) figure 15 . electronic volume level
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 28 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is ?l?, it is necessary to connect external regulator resistor ra between vr and v ss , and rb betwe en v lcd and vr. example: for the following requirements 1. lcd driver voltage, v lcd = 6 v 2. 6 - bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. m aximum current flowing ra, rb = 1 ua from eq. 1 rb 6 = ( 1 + ? ? ? ) x v ev [v] -- ---- ( eq. 3 ) ra from eq. 2 (63 - 32) v ev = ( 1 - ? ? ? ? ? ? ) x 2.1 @ 1. 698 [v] ------ ( eq. 4 ) 162 from requirement 3. 6 ? ? ? ? ? ? = 1 [ua] ------ ( eq. 5 ) ra + rb from equati ons eq. 3, 4 and 5 ra @ 1. 698 [m w ] rb @ 4 . 302 [m w ] the following table shows the range of v lcd depending on the above requirements. table 16. v lcd d epending on electronic volume l evel electronic volume level 0 ....... 32 ....... 63 v lcd 4.53 ....... 6 .00 ....... 7 . 42
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 29 voltage follower circuits v lcd voltage is resistively divided into four voltage levels (v1, v2, v3, v4), and those output impedance are converted by the voltage follower for increasing drive capability. the following table show s the relationship between v1 to v4 level and each duty ratio. table 17. the relationship between v1 to v4 l evel and duty ratio duty r atio duty1 duty0 lcd bias v1 v2 v3 v4 1/5 (4/5) v lcd (3 / 5) v lcd ( 2/ 5) v lcd ( 1/ 5) v lcd 1/33 l l 1/6 (5/6) v lcd (4 / 6) v lcd ( 2/ 6) v lcd ( 1/ 6) v lcd 1/6 (5/6) v lcd (4 / 6) v lcd ( 2/ 6) v lcd ( 1/ 6) v lcd 1/49 l h 1/8 (7/8) v lcd (6 / 8) v lcd ( 2/ 8) v lcd ( 1/ 8) v lcd 1/6 (5/6) v lcd (4 / 6) v lcd ( 2/ 6) v lcd ( 1/ 6) v lcd 1/55 h l 1/8 (7/8) v lcd (6 / 8) v lcd ( 2/ 8) v lcd ( 1/ 8) v lcd 1/ 7 (6/7) v lcd (5 / 7) v lcd ( 2/ 7) v lcd ( 1/ 7) v lcd 1/65 h h 1/9 (8/9) v lcd (7 / 9) v lcd ( 2/ 9) v lcd ( 1/ 9) v lcd high p ower m ode the power supply circuit equipped in the S6B1400X for lcd drive has very low power consumption (in normal mode: hpmb = ? h ? ). if use for l cd panels with large loads, this low - power power supply may cause display quality to degrade. when this occurs, setting the hpmb pin to ? l ? (high power mode) can improve the quality of the display.
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 30 reset circuit setting resetb to ?l? or reset instruction can initialize internal function. when resetb becomes ?l?, the initialized driver has following states . display on / off: off entire display on / off: off (normal) adc select: off (normal) reverse display on / off: off (normal) power control register (vc , vr, vf) = (0, 0, 0) serial interface internal register data clear lcd bias ratio: 1/ 9 (1/65 d uty), 1/8 (1/55 d uty), 1/8 (1/49 d uty), 1 /6 (1/33 d uty) on - chip oscillator off power save release r ead - m odify - write : off shl select: off (normal) static indicat or mode: off static indicator register: (s1, s0) = (0, 0) d isplay start line: 0 (first) column address: 0 page address: 0 regulator resistor select register: (r2, r1, r0) = ( 0 , 1 , 1 ) reference voltage set: off reference voltage control register: ( s v5, s v4, s v3, s v2, s v1, s v0) = (1, 0, 0, 0, 0, 0) test mode release when reset instruction is issued, the initialized driver has following states . r ead - m odify - write : off static indicator mode: off static indicator register: (s1, s0) = (0, 0) shl select: 0 d ispla y start line: 0 (first) column address: 0 page address: 0 regulator resistor select register: (r2, r1, r0) = ( 0 , 1 , 1 ) reference voltage set: off reference voltage control register: ( s v5, s v4, s v3, s v2, s v1, s v0) = (1, 0, 0, 0, 0, 0) test mode release whi le resetb is ?l? or reset instruction is executed, no instruction except read status c ould be accepted. reset status appears at db4. after db4 becomes ?l?, any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initializ e the mpu and this lsi at the same time. the initialization by resetb is essential before used.
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 31 instruction descript ion table 18 . instruction table : don?t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description display on / off 0 0 1 0 1 0 1 1 1 d on turn on / off lcd panel when d on = 0: display off when d on = 1: display on initial display line 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 specify ddram line for com0 set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb read status 0 1 busy adc on /off res etb 0 0 0 0 read the internal status write display data 1 0 write data write data into ddram read display d ata 1 1 read data read data from ddram adc select 0 0 1 0 1 0 0 0 0 adc select seg output direction when adc = 0 : normal direction (seg0 ? seg103) when a dc = 1 : reverse direction (seg103 ? seg0) reverse display on / off 0 0 1 0 1 0 0 1 1 rev select normal / reverse display when rev = 0 : normal display when rev = 1 : reverse display entire display on / off 0 0 1 0 1 0 0 1 0 eon select normal/ entire display on when eon = 0 : normal display. when eon = 1 : entire display on lcd bias select 0 0 1 0 1 0 0 0 1 bias select lcd bias set modify - read 0 0 1 1 1 0 0 0 0 0 set modify - read mode reset modify - read 0 0 1 1 1 0 1 1 1 0 r elease modify - read mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions shl select 0 0 1 1 0 0 shl select com output direction when shl = 0 : normal direction (com0 ? com63) when shl = 1: reverse direction (com63 ? com0) power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation regulator resistor select 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor set r eference v oltage m ode 0 0 1 0 0 0 0 0 0 1 set r eference v oltage m ode set r eference v oltage r egister 0 0 s v5 s v4 s v3 s v2 s v1 s v0 set r eference v oltage r egister set static indicator mode 0 0 1 0 1 0 1 1 0 sm set static indicator mode set static indicator register 0 0 s1 s0 set static indicator register x x 1 0 0 0 0 0 0 0 set data direction & display data length (ddl) x x d7 d6 d5 d4 d3 d2 d1 d0 2 - byte instruction to specify the number o f data bytes (spi mode) power s ave - - - - - - - - - - compound instruction of display off and entire display on
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 32 table 18 . instruction table (continued) : don?t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 des cription nop 0 0 1 1 1 0 0 0 1 1 non - operation command test i nstruction_1 0 0 1 1 1 1 don ? t use this instruction test i nstruction_2 0 0 1 0 0 1 don ? t use this instruction
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 33 display on / off turns the display on or off rs rw db7 db6 d b5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d on d on = 1: display on d on = 0: display off initial display line sets the line address of display ram to determine the initial display line . the ram display data is displayed at the top row (com 0 when s hl = l, com63 when shl = h ) of lcd panel. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 s et page address set s the page address of display data ram from the microprocessor into the page address register. any ram data bit can be accessed when its page address and column address are specified. along with the column address, the page address defines the address of t he display ram to write or read display data. changing the page address doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 p age 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 34 set c olumn address sets the column address of display ram from the microprocessor into the column address register. along with the column address, the column address defines the address of the display ram to write or read display data. when the microprocessor r eads or writes display data to or from display ram, column addresses are automatically incre as ed. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 x y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y6 y5 y4 y3 y2 y1 y0 c olumn address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 1 1 0 102 1 1 0 0 1 1 1 103 read status indicates the internal status of the S6B1400X rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on / off res etb 0 0 0 0 flag description busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy adc indicates the relationship between ram column address and seg ment driver. 0: reverse direction (seg 103 ? seg 0 ), 1: normal direction (seg 0 ? seg 103 ) on / off indicates display on / off status. 0: display on, 1: display off res etb indicates the initialization is in progress by resetb signal. 0: chip is active, 1: ch ip is being reset
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 35 write display data 8 - bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incre as ed by 1 automatically so that the microprocessor ca n continuously write data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data data write set column address set page address optional status column = column + 1 no yes data write continue ? dummy data read set column address set page address optional status column = column + 1 no yes data read continue ? data read column = column + 1 figure 16 . sequence for writing display data figure 17 . sequence for reading display data read display data 8 - bit data from display data ram specified by the column address and page address can be read by this instruction. as the column address is incre as ed by 1 automatically after each this instruction, the microprocessor can continuously read data from th e addressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data adc select (s egment driver direction selec t) changes the relationship between ram column address and segment driver. the direction of segment driver output pins can be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg 0 ? seg 103 ) adc = 1: reverse direction (seg 103 ? seg 0 )
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 36 reverse display on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ?1? ram bit data = ?0? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the reverse display on/off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon = 0: normal di splay eon = 1: e ntire d isplay o n select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 bias lcd bias d uty r atio d uty 1 d uty0 b ias = 0 b ias = 1 1/33 0 0 1/ 6 1/5 1/49 0 1 1/ 8 1/6 1/55 1 0 1/8 1/6 1/65 1 1 1/ 9 1/7 set modify - read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify - read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 37 reset modify - read this instruction cancels the modify - read mode, and makes the column address return to its initial value just before the set modify - read instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess no yes change c omplete ? set column address (n) dummy r ead data r ead data w rite return c olumn a ddress (n) figure 18 . sequence for cursor display reset this instruction resets initial display line, column address, page address, and common output status select to their initial status, but do es not affect the contents of display d ata ram. this instruction cannot initialize the lcd power supply , which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 38 shl select (c ommon output mode select ) com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl : don ? t care shl = 0: normal direction (com 0 ? co m 63 ) shl = 1: reverse direction (com 63 ? com 0 ) power control selects one of eight power circuit functions by using 3 - bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db 2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circ uit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power su pply circuit. refer to the table 15 . rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 (1 + rb / ra) ratio 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4.5 (default) 1 0 0 5.0 1 0 1 5.5 1 1 0 not available 1 1 1 not ava ilable
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 39 r eference v oltage s elect consists of 2 - byte instruction. the 1 st instruction sets reference voltage mode , the 2 nd one updates the contents of reference vol tage register. after second instruction, reference voltage m ode is released. the 1 st instr uction : set reference voltage select m ode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction : set reference voltage r egister rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 sv5 s v4 s v3 s v2 s v1 s v0 s v5 s v4 s v3 s v2 s v1 s v0 refe rence voltage p arameter ( a ) v lcd contrast 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 0 0 0 0 0 32 ( d efault) : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 minimum : : : : : maximum low : : : : : high 2 nd instruction for register setting setting r eference v oltage end 1 st instruction for mode setting setting r eference v oltage start figure 19 . sequence for setting the r eference v oltage
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 40 set static indicator state consists of two bytes instruction. the first byte instruction (set static indicator mode) enables the second byte instruction (set static i ndicator register) to be valid. the first byte sets the static indicator on/off. when it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after settin g the data of indicator register. the 1 st instruction: set static indicator mode (on / off) rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 sm sm = 0: static indicator off sm = 1: static indicator on the 2 nd instruction: set static indicator re gister rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s1 s0 s1 s0 status of static indicator output 0 0 off 0 1 on (about 1 second blinking) 1 0 on (about 0.5 second blinking) 1 1 on (always on)
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 41 set data direction & dis play data length (3 - pin spi mode) consists of two bytes instruction. this command is used in 3 - pin spi mode only (ps = ? l ? and c68 = ? l ? ) . it will be two continuous commands, the first byte control the data direction (write mode only) and inform the lcd driver the second byt e will be number of data bytes will be write. when rs is not used, the display data length instruction is used to indicate that a specified number of display data bytes are to be transmitted. the next byte after the display data string is handled as comma nd data. the 1 st instruction: set data direction (only write mode) rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x 1 0 0 0 0 0 0 0 the 2 nd instruction: set display data length (ddl) register rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x d7 d6 d5 d4 d3 d2 d1 d 0 d7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 nop non - operation i nstruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1 t est i nstruction (t est i nstruction _1 & t est i nstruction_ 2) these are the instruction for ic chip testing. please do not use it. if the test instruction is used by accident, it can be cleared by applying ? 0 ? signal to the resetb in put pin or the reset instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 0 0 1 0 0 1
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 42 power save ( compound insrtuction ) if th e e ntire d isplay on / off instruction is issued during the display off state, S6B1400X enters the power save status to reduce the power consumption to the static power consumption value. according to the status of static indicator mode, power save is entered to one mode of sleep and standby mode. when static indicator mode is on, standby mode is issued . when off, sleep mode is issued. power s ave mode is released by the e ntire d isplay off instruction. sleep mode [oscillator c ircuit: o ff] [lcd power s upply c ircuit: off] [all com / seg o utputs: vss] [consumption c urrent: <2ua] power save off (compound instruction) [entire display o ff ] [static indicator on] 2 b ytes c ommand power save (compound instruction) [display off] [entire display on] static indicator off static indicator on standby mode [oscillator c ircuit: on] [lcd power s upply c ircuit: off] [all com / seg o utputs: vss] [consumption c urrent: <10ua] power save off [entire display o ff ] release sleep mode release standby mode figure 20. power save (compound instruction) - sleep mode this stops all operations in the lcd display system, and as long as the re are no access from the mpu, the consumption current is reduced to a value near the static current. the internal modes during sleep mode are as follows: a. the oscillator circuit and the lcd power supply circuit are halted. b. all liquid crystal driv e circuits are halted, and the segment and common outputs go to the v ss level. - standby mode the duty lcd display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumpt ion current for the static drive. the internal modes are in the following states during standby mode. a. the lcd power supply circuits are halted. the oscillator circuit continues to operate. b. the duty drive system liquid crystal drive circuits are halt ed and the segment and common outputs go to the v ss level. the static drive system does not operate. when a reset command is performed while in standby mode, the system enters sleep mode.
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 43 r eferential instruction setup flow (1) end of initialization waiting for stabilizing the lcd power levels user application setup by internal instructions [adc select] [shl select] [lcd bias select] start of initialization resetb pin = ? h ? waiting for stabilizing the power power o n (v dd - v ss ) keeping the resetb pin = ? l ? user system setup by external pins user lcd p ower setup by internal instructions [voltage converter on] user lcd p ower setup by internal instructions [voltage regulator on] user lcd p ower setup by internal instructions [voltage follower on] user lcd p ower setup by internal instructions [regulator r esistor s elect] [reference voltage r egister s et] waiting for 3 25ms waiting for 3 1ms figure 21 . initializing with the b uilt - in p ower s upply c ircuits
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 44 r eferential instruction setup flow (2) end of initialization write initial display data display data ram addressing by instruction [initial display line] [set page address] [set column address] end of data display turn display on by instruction [display o n / off : don = 1 ] figure 22 . data d isplaying
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 45 r eferential instruction setup flow (3) turn display off by instruction [display o ff ] optional status power off (v dd - v ss ) turn off the voltage follower by internal instructions [voltage follower o ff ] turn off the voltage regulator by internal instructions [voltage regulator o ff ] turn off the voltage converter by internal instructions [voltage converter o ff ] waiting for 3 50ms waiting for 3 1ms waiting for 3 1ms figure 23 . power o ff
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 46 specifications absolute maximum rat ings table 19. absolute maximum ratings parameter symbol rating unit v dd - 0.3 to + 7 .0 v supply voltage range v lcd - 0.3 to + 13 .0 v input voltage range v in - 0.3 to v dd + 0.3 v operating temperature range t op r - 40 to +85 c storage temperature range t str - 55 to +125 c notes: 1. v dd and v lcd are based on v ss = 0v. 2. voltages v lcd 3 v1 3 v2 3 v3 3 v4 3 v ss must always be satisfied. 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 47 dc characteristics table 20. dc characteristics (v s s = 0v, v dd = 2.4 to 3.6v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 2.4 - 3.6 v vdd *1 lcd power voltage (2) v lcd 4.5 - 9.0 v v lcd *2 high v ih 0.8v dd - v dd input voltage low v il v ss - 0.2v dd v *3 high v oh i oh = - 0.5ma 0.8v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0.2v dd v *4 input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a * 5 output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a * 6 lcd driver on resistance r on ta=25 c, v lcd = 8v - 2.0 3.0 k w segn comn * 7 internal f osc 32.7 43.6 54.5 oscillator frequency f cl ta = 25 c duty ratio = 1/65 4.09 5.45 6.81 khz cl *8 3 2.4 - 3.6 voltage converter input voltage vci 4 2.4 - 3.0 v vci reference voltage v ref ta = 25 c - 0.05%/ c 2.04 2.1 2.16 v * 9
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 48 dynamic current consumption when t he b uilt - in p ower c ircuit is on (at o perate m ode) (ta = 25 c ) item symbol condition min. typ. max. unit pin used v dd = 3.0 v, (vci = v dd , 3 times boosting ) v lcd ? v ss = 7.64 v, 1/65 duty ratio, display pattern off, normal power mode - 120 - m a *1 1 v dd = 3.0 v, (vci = v dd , 3 times boosting ) v lcd ? v ss = 7.64 v, 1/65 duty ratio, display pattern checker, normal power mode - 140 - m a *1 1 v dd = 3.0 v, (vci = v dd , 4 times boosting ) v lcd ? v ss = 8.40 v, 1/65 duty ratio, display pattern off, normal power mode - 180 - m a *1 1 dynamic current consumption (2) i dd2 v dd = 3.0 v, (vci = v dd , 4 times boosting ) v lcd ? v ss = 8.40 v, 1/65 duty ratio, display pattern checke r, normal power mode - 200 - m a *1 1 current consumption during power save m ode (ta = 25 c) item symbol condition min. typ. max. unit pin used sleep mode current i dds1 during s leep - - 2 m a standby mode current i dd s 2 during s tandby - - 10 m a
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 49 table 21 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f fr frame frequecncy 1/ 65 on - chip oscillator circuit is used f osc ? ? ? ? 8 f osc ? ? ? ? 2 8 65 f fr 2 1/55 on - chip oscillator circuit is used f osc ? ? ? ? 9 f osc ? ? ? ? 2 9 55 f fr 2 1/49 on - chip oscillator circuit is used f osc ? ? ? ? 10 f osc ? ? ? -- ? 2 10 49 f fr 2 1/33 on - chip oscillator circuit is used f osc ? ? ? ? 15 f osc ? ? ? ? 2 15 33 f fr 2 (f osc : oscillation frequency, f cl : display clo ck frequency, f fr : lcd ac signal frequency ) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is a pplied. *3 . cs1b, cs2, rs, db0 to db7, e_rdb, rw_wrb, resetb, c68 , ps, intrs, hpm b pins . *4 . db0 to db7, fr, frs, cl pins. *5 . cs1b, cs2, rs, db[7:0], e_rdb, rw_wrb, resetb, c68 , ps, intrs, hpm b pins. *6 . applies when the db[7:0], fr, frs and cl pins are i n high impedance. *7 . resistance value when 0.1[ma] is applied during the on status of the output pin segn or comn. ron = d v / 0.1 [k w ] ( d v: voltage change when 0.1[ma] is applied in the on status.) *8 . see table 21 for the relationship between os cillation frequency and frame frequency. * 9. on - chip reference voltage source of the voltage regulator circuit to adjust v lcd . *10,11. applies to the case where the on - chip oscillation circuit is used and no access is made from the mpu. the cu rrent consumption, when the built - in power supply circuit is on or off. the current flowing through voltage regulation resistors (ra and rb) is not included. it does not include the current of the lcd panel capacity, wiring capacity , etc.
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 50 ac characteristics read / write characteristics (8080 - series mpu) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw l 80(r) , t pw l 80(w) t cy80 t ah80 t as80 db 0 to db 7 (write) db 0 to db 7 (read) e_ rd b , rw_ wr b cs1b (cs2) rs t pw h 80(r) , t pw h 80(w) ** t pwl80(w) and t pwl80(r) is specified in the overlapped period when cs1b is low (cs2 is high) and rw_wrb(e_rdb) is low. figure 24. read / write characteristics (8080 - series mpu) (v dd = 2.4 to 3.6v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time rs t cy80 300 - - ns pulse width (wr b ) rw_wrb t pw l 80 (w) t pw h 80 (w) 60 60 - - ns pulse width (rd b ) e_rdb t pw l 80 (r) t pw h 80 (r) 60 60 - - ns data setup time data hold time t ds80 t dh80 40 15 - - ns read access time output disable time db7 t o db0 t acc80 t od80 - 10 - 140 100 ns c l = 100 pf note: 1. the input signal rising time and falling time (tr,tf) is specified at 15ns or less. (tr + tf) < ( t cy80 - t pw l 80 (w) - t pw h 80 (w) ) for write, (tr + tf) < ( t cy80 - t pw l 80 (r) - t pw h 80 (r) ) for read
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 51 read / write characteristics (6800 - series microprocessor) t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t pw h 68(r) , t pw h 68(w) t cy68 t ah68 t as68 db 0 to db 7 (write) e _rdb cs1b (cs2) rs , rw_wrb db 0 to db 7 (read) t pw l 68(r) , t pw l 68(w) ** t pwh68(w) and t pwh68(r) is specified in the overlapped period when cs1b is low (cs2 is high) and e_rdb is high. figure 25. read / write characteristics (6800 - series microprocessor) (v dd = 2.4 to 3.6 v, t a = - 40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs rw_wrb t as68 t ah68 0 0 - - ns system cycle time rs t cy68 300 - - ns data setup time data hold time t ds68 t dh68 40 15 - - ns access tim e output disable time db7 to db0 t acc68 t od68 - 10 - 140 100 ns c l = 100 pf enable pulse width read write e_rdb t pw h 68(r) t pw l 68(r) t pw h 68(w) t pw l 68(w) 120 120 60 60 - - ns note: 1. the input signal rising time and falling time (tr,tf) is specified at 15ns or less. (tr + tf) < ( t cy 6 8 ? t pw h68 (w) ? t pw h6 8 (w) ) for write, (tr + tf) < ( t cy80 ? t pw h6 8 (r) ? t pw l6 8 (r) ) for read
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 52 serial interface characteristics db7 (sid) db6 (sclk) rs cs1b (cs2) t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 26. serial interface characteristics (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 250 100 100 - - - - - - ns address setup time address hold time rs t ass t ahs 150 150 - - - - n s data setup time data hold time db7 (sid) t dss t dhs 100 100 - - - - ns cs1b setup time cs1b hold time cs1b t css t chs 150 150 - - - - ns note: 1. the input signal rising time and falling time (tr,tf) is specified at 15ns or less.
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 53 reset input timin g resetb t rw internal status t r during reset reset complete figure 27. reset input timing (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark reset low pulse width resetb t rw 1.0 - - m s reset time - t r - - 1.0 m s
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 54 reference applicatio ns microp rocessor interface in case of interfacing with 6800 - series (ps = ?h?, c68 = ?h?) db0 to db7 resetb v dd v dd rw e rs cs2 cs1b 6800-series mpu cs1b cs2 rs e_rd b rw_wr b db0 to db7 resetb c68 ps s 6b 07 25 figure 29. i nterfacing with 6800 - series in case of interfacing with 8080 - series (ps = ?h?, c68 = ?l?) db0 to db7 resetb v dd v ss wr b rd b rs cs2 cs1b 8080-series mpu cs1b cs2 rs e_rd b rw_wr b db0 to db7 resetb c68 ps s 6b 07 25 figure 30. i nter facing with 8080 - series
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 55 in case of serial interface with rs pin (ps = ?l?, c68 = ?h ?) open resetb v ss v dd sclk sid rs cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 c68 ps s 6b 07 25 figure 31. 4 pin s erial i nterface in case of serial interface with software command (ps = ?l?, c68 = ? l ?) open resetb v ss v ss sclk sid cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 c68 ps s 6b 07 25 v ss or v dd fig ure 32. 3 pin spi s erial i nterface
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 56 connections between S6B1400X and lcd pan el single chip structure (1/ 6 5 duty configurations) com 32 : com 6 3 coms coms com 0 : com 3 1 seg 103 ........... seg0 s 6b1400x (bottom view) ? a x a ? a x a 64 104 pixels com s com 0 : com 31 com3 2 : com6 3 coms seg 0 ........... seg 103 s 6b1400x (top view) ? a x a ? a x a 64 104 pixels figure 33 . shl = 1, adc = 1 figure 3 4 . shl = 1 , adc = 0 coms com 6 3 : com 32 com 3 1 : com 0 coms seg 103 ........... seg0 s 6b1400x (top view) coms com 6 3 : com 32 com 3 1 : com 0 coms seg0 ............ seg 103 s 6b1400x (bottom view) ? a x a ? a x a 64 104 pixels ? a x a ? a x a 64 104 pixels figure 35 . shl = 0 , adc = 1 figure 36 . shl = 0, adc = 0
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 57 single chip structure (1/ 55 duty configurations) com 37 : com 6 3 coms coms com 0 : com 26 seg 103 ........... seg0 s 6b1400x (bottom view) ? a x a ? a x a 5 4 104 pixels com s com 0 : com 26 com 37 : com 63 coms seg0 ........... seg 103 s 6b1400x (top view) ? a x a ? a x a 5 4 104 pixels figure 37 . shl = 1, adc = 1 figure 38 . shl = 1, adc = 0 coms com 6 3 : com 37 com 26 : com 0 coms seg 103 ........... seg0 s 6b1400x (top view) coms com 6 3 : com 37 com 26 : com 0 coms seg0 ............ seg 103 s 6b1400x (bottom view) ? a x a ? a x a 5 4 104 pixels ? a x a ? a x a 5 4 104 pixels figure 39 . shl = 0 , adc = 1 figure 40 . shl = 0 , adc = 0
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 58 sing le chip structure (1/ 49 duty configurations) com 40 : com 6 3 coms coms com 0 : com 23 seg 103 ........... seg0 s 6b1400x (bottom view) ? a x a ? a x a 48 104 pixels com s com 0 : com 23 com 40 : com6 3 coms seg0 ........... seg 103 s 6b1400x (top view) ? a x a ? a x a 4 8 104 pixels figure 41 . shl = 1 , adc = 1 figure 42 . shl = 1 , adc = 0 coms com 6 3 : com 40 com 23 : com 0 coms seg 103 ........... seg0 s 6b1400x (top view) coms com 6 3 : com 40 com 23 : com 0 coms seg0 ............ seg 103 s 6b1400x (bottom view) ? a x a ? a x a 48 104 pixels ? a x a ? a x a 48 104 pixels figure 43 . shl = 0 , adc = 1 figure 44 . shl = 0 , adc = 0
s6b 1400x spec. ver. 0.0 104 se g / 65 com driver & controller for stn lcd 59 single chip structure (1/ 33 duty configurations) com 48 : com 6 3 coms coms com 0 : com 15 seg 103 ........... seg0 s 6b1400x (bottom view) ? a x a ? a x a 32 104 pixels com s com 0 : com 15 com 48 : com6 3 coms seg0 ........... seg 103 s 6b1400x (top view) ? a x a ? a x a 32 104 pixels figure 45 . shl = 1, adc = 1 figure 46 . shl = 1, adc = 0 coms com 6 3 : com 48 com 15 : com 0 coms seg 103 ........... seg0 s 6b1400x (top view) coms com 6 3 : com 48 com 15 : com 0 coms seg0 ............ seg 103 s 6b1400x (bottom view) ? a x a ? a x a 32 104 pixels ? a x a ? a x a 32 104 pixels figure 47 . shl = 0, adc = 1 figure 48 . shl = 0, adc = 0
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 0.0 S6B1400X 60 S6B1400X application circuit for serial mode n 4 pin spi serial interface lcd panel v lcd v dd vci sclk si d rs cs1b s 6b1400x r es etb v ss vcc port4 port3 port1 port0 mpu reset gnd gnd v cc lcd module commons gnd c1 segments com[0:64] seg[0:103] * c1 is greater than 1 m f + - figure 49. S6B1400X application circuit for 4 pin spi serial interface

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